For various applications, it may be desirable to provide semiconductor devices in which the component transistors have differing threshold voltages. Such semiconductor devices are termed multi-threshold voltage (multi-Vt) devices. For example, a particular integrated circuit may combine SRAM and logic. SRAM transistors typically require a higher Vt than logic transistors. Low threshold voltage (LVt) transistors may thus be used for logic portions of the semiconductor device, while regular threshold voltage (RVt) transistors may be used for the SRAM portions of the semiconductor device. Consequently, multi-Vt semiconductor devices incorporating transistors having differing Vts are desired.
Conventional methods for providing multi-Vt devices rely heavily on a stack including a reactive work function metal (such as Al and/or Ti) placed on top of a mid-gap work function metal (such as TaN and/or TiN) for tuning Vt of the devices. For example, a stack consisting of TiN/TaN/TiN/TiAlC/TiN may be provided on a high dielectric constant layer for use as a transistor gate. The shift in Vt of the transistor depends upon the thicknesses of the layers of stack. The TiN/TaN/TiN/TiAlC/TiN stack typically has a large thickness to provide the desired range of Vt. For example, while functional for close to twenty nanometer spacings, the TiN/TaN/TiN/TiAlC/TiN stack, placed on top of a high dielectric constant layer (a few nanometers thick), may start to merge for replacement metal gate (RMG) spacings on the low teens of nanometers.
The current scaling trend in semiconductor devices has rendered a lower RMG spacing for achieving higher device density. Architectures such as fin field effect transistors (finFETs), gate all around FET (GAA-FET) and replacement metal gate FET (RMG-FET) exist to address certain critical issues at scaled nodes, such as the short channel effect (SCE). However, such architectures do not specifically address issues in multi-Vt devices. Although the use of a work function metal stack works very well for current nodes, at lower spacings at extreme scaled nodes issue arise. As the RMG spacing decreases from scaling, the relatively thick work function metal stack may merge. Stated differently, a work function metal stack that is sufficiently thick to provide the desired shift in Vt may not be capable of fitting into the RMG spacing available given the topology of the underlying surface at extreme scaled nodes. As discussed above, such a stack may start to merge at lower spacings. The variation in Vt (sigma Vt) may also increase as multi-Vt devices are scaled to lower sizes. This is because random variations in the electron work function (eWF) are exacerbated for polycrystalline work function metals at lower sizes.
Mechanisms to shift Vt without increasing the thickness of the work function metal stack and to address variations in eWF exist. However, each method has its drawbacks. Consequently, an improved mechanism for controlling the threshold voltage of a multi-Vt semiconductor device is desired.